Alongside the announcement of the new 7nm Qualcomm Snapdragon 8cx processor for the company’s line of next generation premium tier Always Connected PCs, in the demo room today we saw a wafer of chips built on TSMC’s 7nm.

With this image, we can do one primary thing: work out the die size. Based on our estimates, we can see about 36 chips from top to bottom, and 22.2 chips from side to side. On a standard 300mm wafer, and give a little for the small amount of unused silicon from die to die so they can be cut up, we get a reasonable die size value of 112 square millimeters. This is what we expect to be the upper bound, and the final result may be lower.

That 112 mm2 is from a height of 8.3 mm and a width of 13.5 mm (which technically makes 112.05 mm2, but there is always margin for error here). This would make a total of 532 dies per wafer. There is no mention of defect rate or price per wafer in order to do an analysis of cost per die in manufacturing terms, but if ever get that information it would be an interesting metric.

In the slides, Qualcomm stated that the 8cx has double the transistors. We assume that’s a comparison to the Snapdragon 850, which is an overclocked S845, which had 5.3 billion transistors on the 10nm node. This would make the 8cx at around ~10 billion transistors (to 10.6b) at 112 mm2, or the equivalent of 89-95 million transistors per square millimeter (MTr/mm2). The Snapdragon 845/850 on 10nm would have been 56 MTr/mm2.

*It has come to our attention that the slide listing '2x transistors' was only referencing the size of the graphics of the chip, and not the whole chip itself. The table has been updated.

More information as we get it.

ncG1vNJzZmivp6x7orrAp5utnZOde6S7zGiqoaenZH50gpdwZqqtkaGwsLnMZqqnmaCZv6KzzqdkcZuoYsSissSrZKimXWy7rg%3D%3D